Field of the Invention
The present invention relates to an epitaxial substrate for an electronic device and a method of producing the same and, in particular, to an epitaxial substrate for a HEMT and a method producing the same.
Description of the Related Art
In recent years, HEMT (High electron mobility transistor) has been widely used as high-speed FET (Field effect transistor) as speed required of an IC device increases. Such a FET-type transistor as described above is generally formed, as schematically illustrated in FIG. 1, for example, by laminating a channel layer 22 and an electron supply layer 23 on an insulating substrate 21 and then providing a surface of the electron supply layer 23 with a source electrode 24, a drain electrode 25 and a gate electrode 26. When this transistor device is operated, electrons are moved through the source electrode 24, the electron supply layer 23, the channel layer 22, the electron supply layer 23 and the drain electrode 25 in this order, thereby defining a lateral direction of the device as a main current conducting direction. This movement of electrons in the lateral direction, i.e. the main current conducting direction, is controlled by voltage applied on the gate electrode 26. In a HEMT, electrons generated at a joint interface between the electron supply layer 23 and the channel layer 22 of which band gaps are different from each other can move significantly fast, as compared with electrons in a conventional semiconductor.
An epitaxial substrate formed by epitaxially growing a Group III nitride laminated body on a semiconductor substrate is generally used as an epitaxial substrate for a FET. Examples of such a semiconductor substrate as described above include: a Si substrate having specific resistance exceeding 102 Ω·cm for use to decrease substrate loss which deteriorates device performances, as disclosed in JP 2008-522447 Laid-Open; and a Si substrate having specific resistance of 1.0 to 500 Ω·cm or so for use to decrease leak current to the Si substrate, as disclosed in JP 2003-059948 Laid-Open.
It has been conventionally considered that use of a Si substrate having relatively high specific resistance is preferable, as described above. However, it has been known that, when layers having different specific resistance values are epitaxially grown on a Si substrate having a predetermined resistance, mismatch of lattice constants generally occurs between the Si substrate and the epitaxially-grown layers, whereby warp(s) is generated to alleviate strains. Such warpage of an epitaxial substrate as described above causes maladsorption and/or exposure failure at the stage of a device process.
In order to solve the problems described above, JP 06-112120 Laid-open discloses a technique for decreasing the absolute value of warpage by determining in advance a warping direction in a semiconductor substrate and then adequately growing epitaxial layers on the substrate.
However, the technique disclosed in JP 06-112120 Laid-open simply aims at decreasing the absolute value of warpage of an epitaxial substrate and determines in advance only warpage derived from a slicing process of slicing a wafer from an ingot. Therefore, JP 06-112120 Laid-open cannot control a final warp configuration of the epitaxial substrate in a sufficient manner. JP 06-112120 Laid-open also has a problem that a production process thereof is complicated because it includes a process of determining a warping direction of the semiconductor substrate.